1. Field of the Invention
The present invention relates to a storage apparatus and a computer system including a non-volatile memory and a method for managing the storage apparatus.
2. Description of the Related Art
In recent years, flash memories have been attracting attention as storage media for a digital still camera, a portable computer device, or the like.
The flash memory is a semiconductor memory that uses tunneling or hot-electron injection to cause electrons to pass through a gate insulating film to be injected into a floating gate or a trapping layer so that a threshold of a cell transistor will be changed to store data. In the flash memory, a memory cell can be formed by one transistor using a stacked gate structure, a MNOS structure, or the like, and thus inexpensive and large-capacity memory can be achieved.
Meanwhile, the flash memory has a very slow programming speed, requiring hundreds of microseconds (μs) per cell. Moreover, since overwriting of data is not allowed, an erase operation needs to be performed before programming, and this takes as long as several milliseconds. Such a problem is dealt with by parallel processing for multiple memory cells.
A simple example of a structure of a NAND flash memory, which is a typical example of flash memory, is illustrated in FIG. 1.
In a flash memory 1, a group 2 of cells connected to the same word line, for example, is a unit by which writing and reading are performed at a time, and is called a page. Further, a cell array 3 composed of a plurality of pages is a unit by which erasure is performed at a time, and is called a block. The entire flash memory 1 is composed of a plurality of blocks.
Specifically, ISSCC 2002 Digest, p. 106, session 6.4, for example, describes a 1-Gb NAND flash memory with a page size of 2k bytes and an erasure block size of 128 kB. That is, in one memory array, a group of memory cells with a size of 128k bytes are erased in parallel, and the memory cells are programmed in parallel in units of 2k bytes, so that a programming transfer rate of 10 MB/s is achieved.
In general, each page of the NAND flash has a 64-byte spare area while having a 2k-byte storage area for user data, for example.
A system that uses the NAND flash is able to store various management data, such as parity bits, in this spare area. Writing to this spare area generally needs to be performed simultaneously with writing to the area for the user data, and these two areas are handled as a set.
One noteworthy limitation of the flash memory is that an upper bound of the number of times erasure can be performed is specified.
If the number of times erasure has been performed exceeds the upper bound after repeated rewriting to the same block, data storage in that block ceases to be guaranteed. The upper bound of the number of times erasure can be performed for the above NAND flash is one hundred thousand or less, for example.
With increasing miniaturization of memory cells, variations in the threshold of cell transistors have been increasing, and the operation margin has been deteriorating, resulting in the tendency for the upper bound of the number of times of erasure to decrease further.
Further, in recent years, there has been a tendency for the following new limitations to be placed on the NAND flash in particular, because of changes in internal structure and writing mechanism caused by the miniaturization.
First, a new limitation has been placed on the order in which the pages in the block are written.
Specifically, writing to the pages can be performed in a forward direction, from lower addresses to higher addresses, while writing in an opposite direction is prohibited. For example, once data is written to a certain page, writing of data to lower addresses in the same block is not permitted even when no data has been written to the lower addresses.
Secondly, multiple writing to a page has become difficult. That is, it has become difficult to write data to the same page at two separate times. Therefore, it is becoming difficult to use various techniques formerly used for management of the flash memory, such as marking some bits in the spare area before writing data to the page, or setting a flag in the spare area after data writing.